The present application relates generally to optical devices, and more specifically to methods and structures for aligning and securing an optical fiber to a semiconductor chip such as a photonics chip.
Silicon photonics is a promising technology platform for delivering high-performance optical devices. Silicon photonics relates to the design and development of optical systems that use silicon as an optical medium. In such devices, silicon (Si) is patterned with sub-micron precision into silicon photonic components adapted to receive and process light. Optical fibers are commonly used to transmit optical data to and from a silicon-based photonics chip.
The alignment of optical components such as an individual optical fiber or a fiber array connector (FAC) to a waveguide or other optical component on a photonics chip continues to be a challenge to chip manufacturers. In various alignment schemes, an optical fiber may be positioned onto a chip and aligned with a waveguide or other incumbent structure such as a microelectromechanical system (MEMS) architecture by first machining or etching a groove into the chip, and then placing the optical fiber(s), fiber block or fiber-containing ribbon within the groove. A cover plate may be disposed over the fiber, and an adhesive material may be used to hold the fiber and the cover plate in place.
Processing subsequent to fiber alignment may include a flip-chip module, such as a controlled collapse chip connection (C4) module, or a ball grid array (BGA) laminate to connect the chip to external circuitry such as a printed circuit board. The thermal budget associated with the flip-chip or BGA module, however, including the attendant heating and reflow of solder bumps, may induce thermal strain that causes permanent deformation or even fracture of other on-chip components, including waveguides and/or MEMS structures. In various approaches, thermally-induced deformation of the adhesive layer used to secure the fiber may be transferred to adjacent components, which may have an adverse effect on device performance and manufacturing yield.
Notwithstanding recent developments, it remains a challenge to co-integrate optical fiber alignment and bonding with the thermal budget associated with solder bump reflow without compromising the mechanical integrity of various on-chip structures.